1 /* Unicorn Engine */
2 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2015 */
3 
4 module unicorn.arm64;
5 
6 import unicorn.unicorn;
7 
8 extern(C):
9 
10 /// ARM64 registers
11 enum uc_arm64_reg {
12 	INVALID = 0,
13 
14 	X29,
15 	X30,
16 	NZCV,
17 	SP,
18 	WSP,
19 	WZR,
20 	XZR,
21 	B0,
22 	B1,
23 	B2,
24 	B3,
25 	B4,
26 	B5,
27 	B6,
28 	B7,
29 	B8,
30 	B9,
31 	B10,
32 	B11,
33 	B12,
34 	B13,
35 	B14,
36 	B15,
37 	B16,
38 	B17,
39 	B18,
40 	B19,
41 	B20,
42 	B21,
43 	B22,
44 	B23,
45 	B24,
46 	B25,
47 	B26,
48 	B27,
49 	B28,
50 	B29,
51 	B30,
52 	B31,
53 	D0,
54 	D1,
55 	D2,
56 	D3,
57 	D4,
58 	D5,
59 	D6,
60 	D7,
61 	D8,
62 	D9,
63 	D10,
64 	D11,
65 	D12,
66 	D13,
67 	D14,
68 	D15,
69 	D16,
70 	D17,
71 	D18,
72 	D19,
73 	D20,
74 	D21,
75 	D22,
76 	D23,
77 	D24,
78 	D25,
79 	D26,
80 	D27,
81 	D28,
82 	D29,
83 	D30,
84 	D31,
85 	H0,
86 	H1,
87 	H2,
88 	H3,
89 	H4,
90 	H5,
91 	H6,
92 	H7,
93 	H8,
94 	H9,
95 	H10,
96 	H11,
97 	H12,
98 	H13,
99 	H14,
100 	H15,
101 	H16,
102 	H17,
103 	H18,
104 	H19,
105 	H20,
106 	H21,
107 	H22,
108 	H23,
109 	H24,
110 	H25,
111 	H26,
112 	H27,
113 	H28,
114 	H29,
115 	H30,
116 	H31,
117 	Q0,
118 	Q1,
119 	Q2,
120 	Q3,
121 	Q4,
122 	Q5,
123 	Q6,
124 	Q7,
125 	Q8,
126 	Q9,
127 	Q10,
128 	Q11,
129 	Q12,
130 	Q13,
131 	Q14,
132 	Q15,
133 	Q16,
134 	Q17,
135 	Q18,
136 	Q19,
137 	Q20,
138 	Q21,
139 	Q22,
140 	Q23,
141 	Q24,
142 	Q25,
143 	Q26,
144 	Q27,
145 	Q28,
146 	Q29,
147 	Q30,
148 	Q31,
149 	S0,
150 	S1,
151 	S2,
152 	S3,
153 	S4,
154 	S5,
155 	S6,
156 	S7,
157 	S8,
158 	S9,
159 	S10,
160 	S11,
161 	S12,
162 	S13,
163 	S14,
164 	S15,
165 	S16,
166 	S17,
167 	S18,
168 	S19,
169 	S20,
170 	S21,
171 	S22,
172 	S23,
173 	S24,
174 	S25,
175 	S26,
176 	S27,
177 	S28,
178 	S29,
179 	S30,
180 	S31,
181 	W0,
182 	W1,
183 	W2,
184 	W3,
185 	W4,
186 	W5,
187 	W6,
188 	W7,
189 	W8,
190 	W9,
191 	W10,
192 	W11,
193 	W12,
194 	W13,
195 	W14,
196 	W15,
197 	W16,
198 	W17,
199 	W18,
200 	W19,
201 	W20,
202 	W21,
203 	W22,
204 	W23,
205 	W24,
206 	W25,
207 	W26,
208 	W27,
209 	W28,
210 	W29,
211 	W30,
212 	X0,
213 	X1,
214 	X2,
215 	X3,
216 	X4,
217 	X5,
218 	X6,
219 	X7,
220 	X8,
221 	X9,
222 	X10,
223 	X11,
224 	X12,
225 	X13,
226 	X14,
227 	X15,
228 	X16,
229 	X17,
230 	X18,
231 	X19,
232 	X20,
233 	X21,
234 	X22,
235 	X23,
236 	X24,
237 	X25,
238 	X26,
239 	X27,
240 	X28,
241 
242 	V0,
243 	V1,
244 	V2,
245 	V3,
246 	V4,
247 	V5,
248 	V6,
249 	V7,
250 	V8,
251 	V9,
252 	V10,
253 	V11,
254 	V12,
255 	V13,
256 	V14,
257 	V15,
258 	V16,
259 	V17,
260 	V18,
261 	V19,
262 	V20,
263 	V21,
264 	V22,
265 	V23,
266 	V24,
267 	V25,
268 	V26,
269 	V27,
270 	V28,
271 	V29,
272 	V30,
273 	V31,
274 
275 	//> pseudo registers
276 	PC,			// program counter register
277 
278 	ENDING,		// <-- mark the end of the list of registers
279 
280 	//> alias registers
281 
282 	IP1 = X16,
283 	IP0 = X17,
284 	FP = X29,
285 	LR = X30,
286 }